1. Field of the Invention
The present invention generally relates to a semiconductor memory device including a plurality of memory banks, and more particularly to a nonvolatile semiconductor memory device which reduces the consumption current at the time of operation of each memory bank to stabilize the reading or writing operation of the semiconductor memory device.
2. Description of the Related Art
In recent years, the information society progresses quickly and the mass memory devices have come to be required of the information processing apparatus such as a multiple-purpose IC card incorporating various applications. Moreover, it is the tendency that the use of non-contact type IC cards increases, and the power supply to the IC card can be attained by using the microwave which results in the carrier signal of data to be transmitted. For this reason, there is a demand for the circuit configuration which can reduce the power consumption of internal circuits of the IC card as much as possible.
The power consumption of the IC card is divided roughly into the power consumption of the microprocessor and the power consumption of the memory device. Among these, the internal circuits of the microprocessor are always running, and the consumption current of the microprocessor is almost at a fixed level. Conventionally, by using a regulator, the power is easily supplied from the microwave to the microprocessor for the consumption at the fixed level.
On the other hand, as for the power consumption of the memory device, a series of internal circuits of the memory device start operation when the memory device is accessed. The waveform of the consumed electric current in the memory device does not become fixed. There is the tendency that the peak of the consumed electric current appears at the time of accessing the memory device.
Conventionally, in a DRAM, the memory chip is divided into a plurality of memory banks, and the operation is controlled by each memory-bank unit, thereby reducing the consumed electric current of the whole memory chip.
Moreover, a ferroelectric capacitor acts as a nonvolatile memory element, and it has the characteristics which enable the reading/writing operation of data at high speed. By using such characteristics, the nonvolatile memory device using a ferroelectric capacitor as a memory element (which is called the ferroelectric memory device) is put in practical use. The ferroelectric memory device is widely used for the memory device in the IC card.
FIG. 1A shows the fundamental composition of a memory bank of a conventional ferroelectric memory device, and FIG. 1B shows the waveform of the consumed electric current at the time of operation of the conventional ferroelectric memory device.
FIG. 2 shows the composition of a memory chip which includes a plurality of memory banks. The memory chip 100 includes a plurality of memory banks 10 and peripheral circuits 20. As shown in FIG. 2, the array of memory cells into which the memory chip 100 is divided per word line corresponds to one of the plurality of memory banks 10. The memory bank 10 shown in FIG. 2 is equivalent to the memory bank 10 shown in FIG. 1A.
In the conventional ferroelectric memory device of FIG. 1A, the plate-line driver (PL DRV) 12, the word-line driver (WL DRV) 14, and the sense amplifiers (S/A) 16 are arranged to the memory bank 10. Namely, a plurality of sense amplifiers are provided with respect to one memory block. For example, in the example of FIG. 1A, 32 sense amplifiers (S/A (32X)) are provided with respect to one memory bank.
FIG. 3 shows an example of the circuit configuration which generates a column select signal from the address signal and supplies the column select signal to the memory bank 10 of FIG. 1A.
As shown in FIG. 3, the column select signal generation circuit includes a column pre-decoder 30 and a plurality of column decoders (CDEC) 32-1, 32-2, . . . , 32-X. The number of the column decoders corresponds to the number of the columns of the memory bank 10. The column pre-decoder 30 receives the address signal. A plurality of cell blocks 34 each including the plurality of column decoders are also provided.
The column select signal which is generated by decoding of the address signal is sent to each of the column decoder 32 from the column pre-decoder 30. Each column decoder 32 sets up the value (0 or 1) of a corresponding bit of the received column select signal. The decoded data from each column decoder 32 is outputted as an individual column select signal. The individual column select signal indicates which column of the memory bank 10 at which the memory cell is located is selected. Namely, in the conventional ferroelectric memory device, the individual column select signal is intended to choose a specific one of the columns of the memory bank 10 where the data of the memory cell is accessed.
However, in the conventional ferroelectric memory device, the reading operation is performed for not only the selected cell but also the non-selected cells coupled to the shared word line and plate line that are the same as those of the selected cell. Therefore, in the conventional ferroelectric memory device, the plurality of sense amplifiers are activated at the time of reading of the data.
Thus, in the conventional ferroelectric memory device, once the memory bank 10 is activated, when accessing to each memory cell, all the plurality of sense amplifiers 16 are activated at the same time. For this reason, as shown in FIG. 1B, in the conventional ferroelectric memory device, there is the tendency that a pulse-like peak appears in the waveform of the consumed electric current at the time of the data reading operation.
As described above, in the conventional ferroelectric memory device, there is the tendency that a pulse-like peak appears in the waveform of the consumed electric current at the time of the data reading operation. Hence, there is the problem in that noise is caused by the drop or bumping of the power supply voltage due to the peak current at the time of the data reading operation in the conventional ferroelectric memory device.
Moreover, the fluctuation of the power supply voltage occurs at the time of starting of the sense amplifier activation which amplifies a small difference potential, and there is the problem in that a malfunction of the sense amplifier might be caused. Furthermore, the power supply voltage of the exterior of the memory chip may be affected by the fluctuation of the power supply voltage of the internal circuits of the memory chip, and there is the possibility that a malfunction of other circuits on the system including the memory chip, such as the IC card, takes place.